USHIO Installed a Projection Aligner to Develop 2.5 Glass Interposers for Participating in 2.5D Interposer Consortium Sponsored by Georgiatech 3D Systems Packaging Research Center (GT-PRC)

USHIO INC., today announced that the company installed one unit of a projection aligner dedicated to developing 2.5D glass substrate at the Georgia Tech 3D Systems Packaging Research Center (GT-PRC) on October 31 in 2013, based on conclusion of the partnership agreement related to the interposer development consortium sponsored by GT-PRC. USHIO has already dispatched its engineer and started supporting development of lower-cost glass interposers and packages.

GT-PRC, in partnership with a global industry consortium of end-users and supply chain manufacturers, is developing both 2.5D and 3D glass and organic interposer and package technologies requiring large area patterning, of 1 to 5 µm lithography, on super-thin glass and organic interposer substrates.

To form this partnership agreement, USHIO has leased and installed at GT-PRC, the projection aligner based on the latest stepper model “Square 70” to provide the needed lithography technology for emerging glass and organic interposers. USHIO is now aggressively developing the lithography technology, dedicated to 2.5D and 3D glass and organic interposers, including testing of exposure on large and thin glass substrate as well as achievement of the target resolution required to achieve these finer patterns.

Dr. Rao Tummala, Professor and Director of GT-PRC, commented on the Ushio partnership agreement: “We sincerely appreciate USHIO joining our industry consortium and providing the needed large area lithographic tool. The new Smartphone industry requires exploring a new frontier in electronics systems, ”System Scaling” to go with transistor scaling that we have had since we began Moore’s Law in the 1960s. But the biggest barriers in addressing this new frontier are high throughput manufacturing tools, materials and processes. USHIO’s tool begins to address this need by shrinking the package lithography from current 10 µm to 1 µm in the short-term. We thank USHIO for supporting our leading-edge research and development.” Dr. Venky Sundaram, Program Manager of the Low Cost Glass Interposer and Package (LGIP) program at GT-PRC, added: “USHIO’s large panel lithography tool is a key building block in our strategy to enable glass interposers and packages for pervasive applications at a cost of less than 1c per mm².”

“I believe that our participation in this program will build momentum for USHIO to provide our leading-edge lithography technology for the advanced packaging industry. We also expect that this will help to increase the market share of USHIO’s lithography systems, which have a competitive edge particularly for panel substrates, as well as accelerate the development of peripheral technologies for lithography,” said Toyoharu Inoue, Deputy General Manager of Business Unit I, USHIO INC.

Under the slogan “2.5D Lithography & Packaging Processes,” USHIO will exhibit its products through a panel display and introduce by a stage presentation at USHIO booth No. 4B-601 of SEMICON Japan 2013. Also, during SEMICON Japan 2013, USHIO will hold a release presentation and an exhibitor’s presentation at 11:00–11:20 on December 4 and at 11:30–12:20 on December 6, respectively.

Georgia Tech’s Packaging Research Center (GT-PRC) is well known as the global academic leader pioneering next frontier in electronics by “System Scaling” in contrast to “Transistor Scaling” over the last five decades. It has been pioneering, as a result of 1st NSF ERC at Georgia Tech and in the U.S. in Packaging, an integrated approach to leading-edge strategic research, cross-discipline education of large number graduate students and collaborating with more than 100 global companies, to transfer both the newly-developed technologies in addition to well-educated students to industry, globally.

The current industry programs are Low-cost Glass Interposers and Packages (LGIP); Low-cost Organic Interposers and Packages (LOIP); nanoscale passives such as capacitors and inductors and their integration with actives in ultra-thin 3D IPDs and 3D IPAC packages; off-chip low-temperature Cu interconnections and assembly to 20 µm pitch (I&A); Low CTE package-to-board SMT interconnections and assembly; electrical, mechanical, and thermal design (Design); 3D photonics; MEMs and sensor packaging; and commercialization of ultra-thin organic packages.

GT-PRC has a large team of globally recognized faculty and state-of-the-art cleanroom facilities, including the only cleanroom 300 mm panel facility in the world. The PRC recently celebrated 20 years of successfully running large industry consortia programs with industry-paced milestones and deliverables.

More information is available at www.prc.gatech.edu

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